1. Technical Field
The present invention relates to semiconductor devices, ferroelectric memories, and methods for manufacturing semiconductor devices.
2. Related Art
Memories using ferroelectric (ferroelectric memories) are known to be advantageous over memories using dielectric materials in view of their lower power consumption. Further miniaturization and higher integration of ferroelectric memories are desired. However, in general, the leakage current in a cell of a ferroelectric memory increases as it is further miniaturized. For this reason, in the development of ferroelectric memories, there is a possibility that the advantages of ferroelectric memories as having lower power consumption may be spoiled if priority is given to their miniaturization. Accordingly, the cell size needs to be considered in conjunction with the permissible range of leakage currents and demands for the cell size.
A ferroelectric memory can have a cell structure that is a stacked type or a planar type. FIG. 5 are figures showing a stacked type memory cell structure, wherein (a) shows an upper surface thereof, and (b) shows a cross section thereof. The memory cell shown in FIGS. 5 has a lower electrode 11, a ferroelectric layer 9, and an upper electrode 7. A plug 13 is formed below the lower electrode 11, thereby making an electrical contact between an ion implanted layer (not shown) and the lower electrode 11. Also, a dielectric film 15 composed of SiO2 or the like is provided over the upper electrode 7, and a wiring layer 5 is formed over the dielectric film 15. The plug 13 is formed by embedding a contact hole 3a with a metal such as tungsten or the like. Also, the wiring layer 5 and the upper electrode 7 are electrically connected to each other through a contact hole 3b. 
In the stacked type cell, the contact hole 3b is formed immediately above the contact hole 3a. For this reason, the stacked type cell has an upper surface that is square in which sides a and b in the figure are equal to each other. The structure of the illustrated stacked type cell is more advantageous in reducing the occupancy area of the cell than the planar type in which two contact holes are formed at positions separated from each other. For this reason, in view of further miniaturization of cells, it may be desirous to adopt stacked type cells in products. However, the stacked type cell has a structure in which the leak current is larger than that of the planar type cell, and if it is miniaturized to a desired size, its power consumption would reach a level unsuitable for practical use.
For this reason, in prior art, miniaturization of planar type cells, which are advantageous in view of power consumption, is examined. As the prior art, for example, a conventional technology described in Japanese Laid-open Patent Application HEI 10-229168 may be enumerated. HEI 10-229168 describes adjusting the positions of contact holes of planar type cells to thereby reduce the area occupied by the cells, and increase the degree of integration. Also, Japanese Laid-open Patent Application HEI 10-65113 proposes a technology to reduce the leakage current of planar type cells by providing an upper electrode and a lower electrode with different sizes.
However, the conventional technologies described above all use planar type cells, and intend to improve the same. For this reason, it is difficult to miniaturize these cells to a size that is equal to a cell size that can be achieved when stacked type cells are adopted. The present invention has been made in view of the problems described above, and its object is to provide semiconductor devices and ferroelectric memories which are of a stacked type, but whose leakage current is permissible even when they are miniaturized to a necessary size, and a method for manufacturing such semiconductor devices.